Commonly assigned U.S. patent application Ser. No. 09/275,610 is incorporated for its showing of a PCI bus bridge system for processing requests from multiple attached hosts.
This invention relates to the transfer of write data across a PCI bus, and, more particularly, to accommodating the transfer of bursts of write data in an environment of a plurality of agents attached to the PCI bus.
The Peripheral Component Interconnect (PCI) bus system is a high-performance expansion bus architecture which offers a low latency path employing PCI bridges through which a host processor may directly access PCI devices. In a multiple host environment, a PCI bus system may include such functions as data buffering and PCI central functions such as arbitration over usage of the bus system.
The incorporated ""610 application describes an example of a complex PCI bus system for providing a connection path between a secondary PCI bus, to which are attached a plurality of agents, such as channel adapters, and at least one primary bus to which is attached a peripheral device server. The incorporated ""610 application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here. Complex PCI bus systems, such as that of the incorporated ""610 application, employ arbitration between commands from the attached channel adapters on the PCI bus system to manage the usage of the bus system in an efficient manner.
Computer data storage systems may employ PCI bus systems to provide fast data storage from host processors, such as network servers, via channel adapters and the PCI bus system, to attached storage servers having storage devices, cache storage, or non-volatile cache storage. It is advantageous to provide data storage that operates at relatively fast speeds which approach or match the speeds of the host processors, or that release the host processors, such that the host processors are not slowed. The incorporated ""610 application additionally defines many of the terms employed herein, and such definitions are also available from publications provided by the PCI Special Interest Group, and will not be repeated here.
Typically, such channel adapters transfer write data in bursts of multiple contiguous words, where a word comprises data bits which are equal to the width of the data bus. In a PCI bus system, the write data is received from the channel adapters at the secondary PCI bus by one or more PCI bus adapters. A PCI bus adapter has a command queue which queues the operation commands on a FIFO basis, and the associated address and data in a queue buffer. Preferably, the command queue and queue buffer are sufficiently large that a single write command, the address to which the write data is directed, and the data burst may be queued at once. This arrangement allows the data transfer to be conducted efficiently.
The PCI bus adapter has the ability to issue a xe2x80x9cType B disconnectxe2x80x9d action if the queue buffer is full and the adapter is unable to conduct xe2x80x9ctarget readyxe2x80x9d pacing, which causes the requesting agent, such as a channel adapter, to disconnect and return the bus to an idle state. If the request is a burst write command, and the PCI bus adapter is the target of that data, the amount of data stored at the PCI bus target is the space available in the target""s queue buffer when the burst write began. If the space available was two locations in the buffer, when the amount of data stored in the queue buffer would be one, because the address and command would take one location and the data another. As is known to those of skill in the art, if multiple commands are in the command queue, the PCI bus adapter is unable to conduct xe2x80x9ctarget readyxe2x80x9d pacing, and the burst write would be stored as a command in the command queue and the address and a single word of data in the queue buffer.
If for example, the PCI bus target has queued several single word write commands preceding the attempted burst write, as it executes the write commands from the command queue, it makes room for an additional single word write command. The requesting agent (channel adapter) granted access to the PCI bus and targeting this agent, will be allowed to write just one word of data before receiving another disconnect, because the target""s queue buffer went full again and the target was unable to conduct xe2x80x9ctarget readyxe2x80x9d pacing. This condition is called data fracturing and could be repeated for the entire write burst size. If, as an example, the requesting agent wanted to provide a write burst of 128 words, the burst could be broken up into 128 single word operations. Even worse, there could be several requesting agents on the PCI bus attempting to execute a burst write to this same target, and their bursts could all be broken up into single word writes. The resultant performance of the PCI bus system is severely degraded in this circumstance, as is the performance of the attached requesting agents and the agent (such as the data storage system) that is the destination for the data, because single word operations on the PCI bus are much slower than PCI burst operations.
An object of the present invention is to limit fracturing of PCI burst write operations and thereby enhance the effective PCI bandwidth.
In a PCI bus system for transferring write data in the form of write data bursts comprising a plurality of contiguous words, a system and method are disclosed for limiting fracturing of burst write data. The PCI bus system has at least one PCI bus for coupling at least one PCI data source to the PCI bus system, and a PCI bus target, such as a PCI bus adapter, coupled to the PCI bus for receiving and transferring the write data from the PCI data source, the PCI bus target queuing operation commands in a command queue.
The system for limiting fracturing of the write data comprises fracture detection logic which monitors the PCI bus target to sense fracturing of the write data. Queue level detection logic is employed to monitor completion of the queued operation commands of the PCI bus target. A bus arbiter is responsive to the fracture level detection logic sensing the fracturing of write data by the target, and blocks access to the PCI bus. The bus arbiter is then responsive to the command queue level detection logic indicating, subsequent to the blocking, that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to allow the PCI data source to complete the burst write operation without fracturing.
For a fuller understanding of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.